1. Field of the Invention
The present invention relates to non-volatile semiconductor memories and, more particularly, to electrically erasable programmable read-only memories with large storage capacity.
2. Description of the Related Art
With the increasing needs for high performance and reliability of digital computer systems, the development of a semiconductor memory has strongly been demanded that has enough storage capacity to replace an existing non-volatile data storage device, such as a magnetic floppy disk unit, for computers. As compared with magnetic disk storage devices, such as a floppy disk unit and a hard disk unit, a presently available electrically erasable programmable semiconductor read-only memory is reliable and fast in data writing/reading speed. However, the electrically erasable programmable semiconductor read-only memory is not still large in data storage capacity enough to replace the above magnetic data storage devices.
In a conventional electrically erasable programmable read-only memory (abbreviated to "EEPROM" hereinafter), each memory cell is typically composed of two transistors and data is randomly written or erased one byte at a time. Hence, such high-density integration of the EEPROM as provides large storage capacity enough to replace the peripheral data storage devices will be difficult to expect.
Recently, as a non-volatile semiconductor memory which is integrated at high density and thus has a large storage capacity, an erasable programmable read-only memory has been developed that has a "NAND type cell" structure. This type of memory device is typically designed such that: (1) each memory cell utilizes one transistor having a floating gate and a control gate; and (2) a single contact is provided between an array of memory cells arranged on a substrate to constitute an "NAND cell structure" and a corresponding bit line. Hence, as compared with the conventional EEPROM, the area occupied by memory cells can considerably be reduced and thus the integration density can be improved.
However, the conventional NAND cell type EEPROM is suffering from problems of the large current dissipation and the surface voltage drop (known as "surface breakdown") which occurs in the memory cells of the NAND cell blocks at the time of data writing. For example, according to conventional devices, the data writing into a selected memory cell is achieved by injecting electrons from a chip substrate into the floating gate of the memory cell through hot-electron injection. The injection of electrons through hot-electron injection undesirably increases the current dissipation in EEPROM. Semiconductor diffusion layers serving as drains and sources of series-arrayed cell transistors of a selected NAND cell block are directly formed in a surface portion of a chip substrate of an opposite conductivity type. When a boosted potential is applied to sources and drains of the remaining nonselected cell transistors in order to write data into a selected memory cell transistor of the NAND cell block, the surface breakdown will occur in the diffusion layers of the remaining transistors. The surface breakdown in the diffusion layers not only prevents effective data writing into the selected cell but also causes a variation of the thresholds of the nonselected cells. This will result in degradation of the operational reliability of the EEPROM.